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final publication# 20420 rev: b amendment/ +1 issue date: june 1998 com?: -5/7/10/12/15 ind: -7/10/12/14/18 mach 111-5/7/10/12/15 high-performance ee cmos programmable logic distinctive characteristics u 44 pins in plcc and tqfp u 32 macrocells u 5 ns t pd commercial, 7.5 ns t pd industrial u 182 mhz f cnt u 32 i/os; 4 dedicated inputs/clocks; 2 dedicated inputs u 32 flip-?ps; 4 clock choices u 2 ?alce26v16?blocks u speedlocking for guaranteed ?ed timing u bus-friendly inputs and i/os u peripheral component interconnect (pci) compliant (-5/-7/-10/-12) u programmable power-down mode u safe for mixed supply voltage system designs u pin-compatible with the mach211 general description the mach111 is a member of vantis?high-performance ee cmos mach 1 & 2 families. this device has approximately three times the logic macrocell capability of the popular palce22v10 without loss of speed. the mach111 consists of two pal blocks interconnected by a programmable switch matrix. the two pal blocks are essentially ?alce26v16?structures complete with product-term arrays and programmable macrocells, which can be programmed as high speed or low power. the switch matrix connects the pal blocks to each other and to all input pins, providing a high degree of connectivity between the fully connected pal blocks. this allows designs to be placed and routed ef?iently. the mach111 macrocell provides either registered or combinatorial outputs with programmable polarity. if a registered con?uration is chosen, the register can be con?ured as d-type or t- type to help reduce the number of product terms. the register type decision can be made by the designer or by the software. all macrocells can be connected to an i/o cell. if a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the i/o pin for use as an input. vantis offers software design support for mach devices through its own development system and device ?ters integrated into third-party cae tools. platform support extends across pcs, sun and hp workstations under advanced operating systems such as windows 3.1, windows 95 and nt, sunos and solaris, and hpux.
2 MACH111-5/7/10/12/15 machxl software is a complete development system for the pc, supporting vantis' mach devices. it supports design entry with boolean and behavioral syntax, state machine syntax and truth tables. functional simulation and static timing analysis are also included in this easy-to- use system. this development system includes high-performance device ?ters for all mach devices. the same ?ter technology included in machxl software is seamlessly incorporated into third-party tools from leading cae vendors such as synario, viewlogic, mentor graphics, cadence and minc. interface kits and machxl con?urations are also available to support design entry and veri?ation with other leading vendors such as synopsys, exemplar, orcad, synplicity and model technology. these machxl con?urations and interfaces accept edif 2.0.0 netlists, generate jedec ?es for mach devices, and create industry-standard sdf, vital-compliant vhdl and verilog output ?es for design simulation. vantis offers in-system programming support for mach devices through its machpro software enabling mach device programmability through jtag compliant ports and easy-to-use pc interface. additionally, machpro generated vectors work seamlessly with hp3070, genrad and teradyne testers to program mach devices or test them for connectivity. all mach devices are supported by industry standard programmers available from a number of vendors. these programmer vendors include advin systems, bp microsystems, data i/o corporation, hi-lo systems, sms gmbh, stag house, and system general.
MACH111-5/7/10/12/15 3 block diagram 52 x 70 and logic array and logic allocator i/o 0 ?i/o 15 i/o cells macrocells switch matrix 16 oe 20420b-1 16 16 16 26 2 52 x 70 and logic array and logic allocator i/o 16 ?i/o 31 clk 3 /i 5 clk 1 /i 2 i/o cells macrocells oe 26 2 16 16 16 16 4 2 4 4 i 0 -i 1 /clk 0 i 3 -i 4 /clk 2 block a block b 4 4
4 MACH111-5/7/10/12/15 connection diagram top view 44-pin plcc note: pin-compatible with the mach211sp and mach211. pin designations clk/i = clock or input gnd = ground i = input i/o = input/output v cc = supply voltage block a block b 1 44 43 42 5 4 3 2 641 40 7 8 9 10 11 12 13 14 15 16 17 23 24 25 26 19 20 21 22 18 27 28 39 38 37 36 35 34 33 32 31 30 29 i/o5 i/o6 i/o7 i0 clk0/i1 gnd clk1/i2 i/o8 i/o9 i/o10 i/o11 i/o27 i/o26 i/o25 i/o24 clk3/i5 gnd clk2/i4 i3 i/o23 i/o22 i/o21 i/o12 i/o13 i/o14 i/o15 v cc gnd i/o16 i/o17 i/o18 i/o19 i/o20 i/o4 i/o3 i/o2 i/o1 i/o0 gnd v cc i/o31 i/o30 i/o29 i/o28 20420b-2
MACH111-5/7/10/12/15 5 connection diagram top view 44-pin tqfp note: pin-compatible with the mach211sp. pin designations clk/i = clock or input gnd = ground i = input i/o = input/output v cc = supply voltage block b block a i/o12 i/o13 i/o14 i/o15 v cc gnd i/o16 i/o17 i/o18 i/o19 i/o20 i/o4 i/o3 i/o2 i/o1 i/o0 gnd v cc i/o31 i/o30 i/o29 i/o28 i/o27 i/o26 i/o25 i/o24 clk3/i5 gnd clk2/i4 i3 i/o23 i/o22 i/o21 i/o5 i/o6 i/o7 i0 clk0/i1 gnd clk1/i2 i/o8 i/o9 i/o10 i/o11 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 20420b-3
6 MACH111-5/7/10/12/15 (com?) ordering information commercial products vantis programmable logic products for commercial applications are available with several ordering options. the order number (valid combination) is formed by a combination of: valid combinations the valid combinations table lists con?urations planned to be supported in volume for this device. consult the local vantis sales of?e to con?m availability of speci? valid combinations and to check on newly released combinations. family type mach = macro array cmos high-speed mach 111 -5 j c device number 111 = 32 macrocells, 44 pins, power-down option, bus-friendly inputs operating conditions c = commercial (0 c to +70 c) package type j = 44-pin plastic leaded chip carrier (pl 044) v = 44-pin thin quad flat pack (pqt044) speed -5 = 5 ns t pd -7 = 7.5 ns t pd -10 = 10 ns t pd -12 = 12 ns t pd -15 = 15 ns t pd valid combinations MACH111-5 jc, vc mach111-7 mach111-10 mach111-12 mach111-15
mach111-7/10/12/14/18 (ind) 7 ordering information industrial products vantis programmable logic products for industrial applications are available with several ordering options. the order number (valid combination) is formed by a combination of: valid combinations the valid combinations table lists con?urations planned to be supported in volume for this device. consult the local vantis sales of?e to con?m availability of speci? valid combinations and to check on newly released combinations. device number 111 = 32 macrocells, 44 pins, power-down option, bus-friendly inputs family type mach = macro array cmos high-speed mach 111 -7 j i operating conditions i = industrial (?0 c to +85 c) package type j = 44-pin plastic leaded chip carrier (pl 044) speed -7 = 7.5 ns t pd -10 = 10 ns t pd -12 = 12 ns t pd -14 = 14 ns t pd -18 = 18 ns t pd valid combinations mach111-7 ji mach111-10 mach111-12 mach111-14 mach111-18
8 MACH111-5/7/10/12/15 functional description the mach111 consists of two pal blocks connected by a switch matrix. there are 32 i/o pins and 2 dedicated input pins feeding the switch matrix. these signals are distributed to the two pal blocks for ef?ient design implementation. there are four clock pins that can also be used as dedicated inputs. the pal blocks each pal block in the mach111 (figure 1) contains a 64-product-term logic array, a logic allocator, 16 macrocells, and 16 i/o cells. the switch matrix feeds each pal block with 26 inputs. this makes the pal block look effectively like an independent ?alce26v16. there are four additional output enable product terms in each pal block. for purposes of output enable, the 16 i/o cells are divided into 2 banks of 8 macrocells. each bank is allocated two of the output enable product terms. an asynchronous reset product term and an asynchronous preset product term are provided for ?p-?p initialization. all ?p-?ps within the pal block are initialized together. the switch matrix the mach111 switch matrix is fed by the inputs and feedback signals from the pal blocks. each pal block provides 16 internal feedback signals and 16 i/o feedback signals. the switch matrix distributes these signals back to the pal blocks in an ef?ient manner that also provides for high performance. the design software automatically con?ures the switch matrix when ?ting a design into the device. the product-term array the mach111 product-term array consists of 64 product terms for logic use, and 6 special-purpose product terms. four of the special-purpose product terms provide programmable output enable; one provides asynchronous reset, and one provides asynchronous preset. two of the output enable product terms are used for the ?st eight i/o cells; the other two control the last eight macrocells. the logic allocator the logic allocator in the mach111 takes the 64 logic product terms and allocates them to the 16 macrocells as needed. each macrocell can be driven by up to 12 product terms. the design software automatically con?ures the logic allocator when ?ting the design into the device. table 1 illustrates which product term clusters are available to each macrocell within a pal block. refer to figure 1 for cluster and macrocell numbers. table 1. logic allocation output macrocell available clusters output macrocell available clusters m 0 c 0 , c 1 m 8 c 8 , c 9 m 1 c 0 , c 1 , c 2 m 9 c 8 , c 9 , c 10 m 2 c 1 , c 2 , c 3 m 10 c 9 , c 10 , c 11 m 3 c 2 , c 3 , c 4 m 11 c 10 , c 11 , c 12 m 4 c 3 , c 4 , c 5 m 12 c 11 , c 12 , c 13 m 5 c 4 , c 5 , c 6 m 13 c 12 , c 13 , c 14 m 6 c 5 , c 6 , c 7 m 14 c 13 , c 14 , c 15 m 7 c 6 , c 7 m 15 c 14 , c 15
MACH111-5/7/10/12/15 9 the macrocell the mach111 macrocells can be con?ured as either registered or combinatorial, with programmable polarity. the macrocell provides internal feedback whether con?ured as registered or combinatorial. the ?p-?ps can be con?ured as d-type or t-type, allowing for product-term optimization. the ?p-?ps can individually select one of four clock pins, which are also available as data inputs. the registers are clocked on the low-to-high transition of the clock signal. the ?p-?ps can also be asynchronously initialized with the common asynchronous reset and preset product terms. the i/o cell the i/o cell in the mach111 consists of a three-state output buffer. the three-state buffer can be con?ured in one of three ways: always enabled, always disabled, or controlled by a product term. if product term control is chosen, one of two product terms may be used to provide the control. the two product terms that are available are common to eight i/o cells. within each pal block, two product terms are available for selection by the ?st eight three-state outputs; two other product terms are available for selection by the last eight three-state outputs. speedlocking for guaranteed fixed timing the unique mach 1 & 2 architecture is designed for high performance? metric that is met in both raw speed, but even more importantly, guaranteed ?ed speed. using the design of the central switch matrix, the mach111 product offers the speedlocking feature, which allows a stable ?ed pin-to-pin delay, independent of logic paths, routing resources and design re?s for up to 12 product terms per output. other non-vantis cplds incur serious timing delays as product terms expand beyond their typical 4 or 5 product-term limits. speed and speedlocking combine for continuous, high performance required in today's demanding designs. bus-friendly inputs and i/os the mach111 inputs and i/os include two inverters in series which loop back to the input. this double inversion reinforces the state of the input and pulls the voltage away from the input threshold voltage. unlike a pull-up, this con?uration cannot cause contention on a bus. for an illustration of this con?uration, please turn to the input/output equivalent schematics section. pci compliant the MACH111-5/7/10/12 is fully compliant with the pci local bus speci?ation published by the pci special interest group. the MACH111-5/7/10/12? predictable timing ensures compliance with the pci ac speci?ations independent of the design. power-down mode the mach111 features a programmable low-power mode in which individual signal paths can be programmed as low power. these low-power speed paths will be slightly slower than the non-low-power paths. this feature allows speed critical paths to run at maximum frequency while the rest of the paths operate in the low-power mode, resulting in power savings of up to 50%. safe for mixed supply voltage system designs the mach111 is safe for mixed supply voltage system designs. the 5-v device will not overdrive 3.3-v devices above the output voltage of 3.3 v, while it accepts inputs from other 3.3-v devices. thus, the mach111 provides easy-to-use mixed-voltage design compatibility.
10 MACH111-5/7/10/12/15 0 4 8 12 16 20 24 28 40 32 43 36 0 4 8 12 16 20 24 28 40 32 43 36 i/o cell i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o switch matrix output enable output enable asynchronous reset asynchronous preset output enable output enable clk 16 i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell 16 output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell 2 47 51 47 51 0 logic allocator 63 c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 m 3 m 6 m 5 m 4 m 2 m 1 m 0 m 9 m 8 m 7 m 10 m 11 m 12 m 13 m 14 m 15 20420b-4 figure 1. mach111 pal block
MACH111-5/7/10/12/15 (com?) 11 absolute maximum ratings storage temperature . . . . . . . . . . . . . ?5 c to +150 c ambient temperature with power applied . . . . . . . . . . . . . ?5 c to +125 c device junction temperature . . . . . . . . . . . . . +150 c supply voltage with respect to ground . . . . . . . . . . . . . . ?.5 v to +7.0 v dc input voltage . . . . . . . . . . . .?.5 v to v cc + 0.5 v dc output or i/o pin voltage . . . . . . . . . . . . . ?.5 v to v cc + 0.5 v static discharge voltage . . . . . . . . . . . . . . . . . 2001 v latchup current (t a = 0 c to 70 c) . . . . . . . . . 200 ma stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air . . . . . . . . . . . . . . . 0 c to +70 c supply voltage (v cc ) with respect to ground . . . . . . . . . +4.75 v to +5.25 v operating ranges de?e those limits between which the functionality of the device is guaranteed. dc characteristics over commercial operating ranges notes: 1. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be shorted at a time. duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. 4. measured with a 16-bit up/down counter program in low-power mode. this pattern is programmed in each pal block and is capable of being enabled and reset. parameter symbol parameter description test conditions min typ max unit v oh output high voltage i oh = ?.2 ma, v cc = min, v in = v ih or v il 2.4 v v ol output low voltage i ol = 16 ma, v cc = min, v in = v ih or v il 0.5 v v ih input high voltage guaranteed input logical high voltage for all inputs (note 1) 2.0 v v il input low voltage guaranteed input logical low voltage for all inputs (note 1) 0.8 v i ih input high current v in = 5.25 v, v cc = max (note 2) 10 m a i il input low current v in = 0 v, v cc = max (note 2) ?0 m a i ozh off-state output leakage current high v out = 5.25 v, v cc = max v in = v ih or v il (note 2) 10 m a i ozl off-state output leakage current low v out = 0 v, v cc = max v in = v ih or v il (note 2) ?0 m a i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) ?0 ?60 ma i cc supply current (static) v cc = 5 v, t a = 25 c, f = 0 mhz (note 4) 40 ma supply current (active) v cc = 5 v, t a = 25 c, f = 1 mhz (note 4) 45 ma
12 MACH111-5/7/10/12/15 (com?) capacitance (note 1) switching characteristics over commercial operating ranges (note 2) notes: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modi?d whe re frequency may be affected. 2. see switching test circuit for test conditions. 3. if a signal is powered-down, this parameter must be added to its respective high-speed parameter. parameter symbol parameter description test conditions typ unit c in input capacitance v in = v cc ?.5 v v cc = 5.0 v, t a = 25 c f = 1 mhz 6pf c out output capacitance v out = 2.0 v 8 pf paramete r symbol parameter description -5 -7 -10 -12 -15 unit min max min max min max min max min max t pd input, i/o, or feedback to combinatorial output 5 7.5 10 12 15 ns t s setup time from input, i/o, or feedback to clock d-type 3.5 5.5 6.5 7 10 ns t-type 4 6.5 7.5 8 11 ns t h register data hold time 0 0 0 0 0 ns t co clock to output 3.5 5 6 8 10 ns t wl clock width low 2.5 3 5 6 6 ns t wh high 2.5 3 5 6 6 ns f max maximum frequency (note 1) external feedback 1/(t s + t co ) d-type 143 95 80 66.7 50 mhz t-type 133 87 74 62.5 47.6 mhz internal feedback (f cnt ) d-type 182 133 100 76.9 66.6 mhz t-type 167 125 91 71.4 55.5 mhz no feedback 1/(t wl + t wh ) 200 166.7 100 83.3 83.3 mhz t ar asynchronous reset to registered output 7.5 9.5 11 16 20 ns t arw asynchronous reset width (note 1) 4.5 5 7.5 12 15 ns t arr asynchronous reset recovery time 4.5 5 7.5 8 10 ns t ap asynchronous preset to registered output 7.5 9.5 11 16 20 ns t apw asynchronous preset width (note 1) 4.5 5 7.5 12 15 ns t apr asynchronous preset recovery time (note 1) 4.5 5 7.5 8 10 ns t ea input, i/o, or feedback to output enable 7.5 9.5 10 12 15 ns t er input, i/o, or feedback to output disable 7.5 9.5 10 12 15 ns t lp t pd increase for powered-down macrocell (note 3) 10 10 10 10 10 ns t lps t s increase for powered-down macrocell (note 3) 77777ns t lpco t co increase for powered-down macrocell (note 3) 33333ns t lpea t ea increase for powered-down macrocell (note 3) 10 10 10 10 10 ns
mach111-7/10/12/14/18 (ind) 13 absolute maximum ratings storage temperature . . . . . . . . . . . . . ?5 c to +150 c ambient temperature with power applied . . . . . . . . . . . . . ?5 c to +125 c device junction temperature . . . . . . . . . . . . . +150 c supply voltage with respect to ground . . . . . . . . . . ?.5 v to +7.0 v dc input voltage . . . . . . . . . . . .?.5 v to v cc + 0.5 v dc output or i/o pin voltage. . . . . . . . . . . ?.5 v to v cc + 0.5 v static discharge voltage . . . . . . . . . . . . . . . . . 2001 v latchup current (t a = ?0 c to +85 c) . . . . . . 200 ma stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device r eliability. operating ranges industrial (i) devices temperature (t a ) operating in free air . . . . . . . . . . . . . . ?0 c to +85 c supply voltage (v cc ) with respect to ground . . . . . . . . . . . +4.5 v to +5.5 v operating ranges de?e those limits between which the functionality of the device is guaranteed. dc characteristics over industrial operating ranges notes: 1. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be shorted at a time. duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. 4. measured with a 16-bit up/down counter program in low-power mode. this pattern is programmed in each pal block and is capable of being enabled and reset. parameter symbol parameter description test conditions min typ max unit v oh output high voltage i oh = ?.2 ma, v cc = min, v in = v ih or v il 2.4 v v ol output low voltage i ol = 16 ma, v cc = min, v in = v ih or v il 0.5 v v ih input high voltage guaranteed input logical high voltage for all inputs (note 1) 2.0 v v il input low voltage guaranteed input logical low voltage for all inputs (note 1) 0.8 v i ih input high current v in = 5.25 v, v cc = max (note 2) 10 m a i il input low current v in = 0 v, v cc = max (note 2) ?0 m a i ozh off-state output leakage current high v out = 5.25 v, v cc = max v in = v ih or v il (note 2) 10 m a i ozl off-state output leakage current low v out = 0 v, v cc = max v in = v ih or v il (note 2) ?0 m a i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) ?0 ?60 ma i cc supply current (static) v cc = 5 v, t a = 25 c, f = 0 mhz (note 4) 40 ma supply current (active) v cc = 5 v, t a = 25 c, f = 1 mhz (note 4) 45 ma
14 mach111-7/10/12/14/18 (ind) capacitance (note 1) switching characteristics over industrial operating ranges (note 2) notes: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modi?d whe re frequency may be affected. 2. see switching test circuit for test conditions. 3. if a signal is powered-down, this parameter must be added to its respective high-speed parameter. parameter symbol parameter description test conditions typ unit c in input capacitance v in = v cc ?.5 v v cc = 5.0 v, t a = 25 c f = 1 mhz 6pf c out output capacitance v out = 2.0 v 8 pf parameter symbol parameter description -7 -10 -12 -14 -18 unit min max min max min max min max min max t pd input, i/o, or feedback to combinatorial output 7.5 10 12 14 18 ns t s setup time from input, i/o, or feedback to clock d-type 5.5 6.5 7 8.5 12 ns t-type 6.5 7.5 8 10 13.5 ns t h register data hold time 0 0 0 0 0 ns t co clock to output 5 6 8 10 12 ns t wl clock width low 3 5 6 6 7.5 ns t wh high 3 5 6 6 7.5 ns f max maximum frequency (note 1) external feedback 1/(t s + t co ) d-type 95 80 66.7 54 40 mhz t-type 87 74 62.5 50 38 mhz internal feedback (f cnt ) d-type 133 100 76.9 61.5 53 mhz t-type 125 91 71.4 57 44 mhz no feedback 1/(t wl + t wh ) 166.7 100 83.3 83.3 61.5 mhz t ar asynchronous reset to registered output 9.5 11 16 19.5 24 ns t arw asynchronous reset width (note 1) 5 7.5 12 14.5 18 ns t arr asynchronous reset recovery time 5 7.5 8 10 12 ns t ap asynchronous preset to registered output 9.5 11 16 19.5 24 ns t apw asynchronous preset width (note 1) 5 7.5 12 14.5 18 ns t apr asynchronous preset recovery time 5 7.5 8 10 12 ns t ea input, i/o, or feedback to output enable (note 1) 9.5 10 12 14.5 18 ns t er input, i/o, or feedback to output disable (note 1) 9.5 10 12 14.5 18 ns t lp t pd increase for powered-down macrocell (note 3) 10 10 10 10 10 ns t lps t s increase for powered-down macrocell (note 3) 77777ns t lpco t co increase for powered-down macrocell (note 3) 33333ns t lpea t ea increase for powered-down macrocell (note 3) 10 10 10 10 10 ns
MACH111-5/7/10/12/15 15 typical current vs. voltage (i-v) characteristics v cc = 5.0 v, t a = 25 c -0.8 -0.6 -0.4 .2 -0.2 -1.0 .4 .6 1.0 .8 60 40 20 -20 -40 80 -60 -80 20420b-5 output, low v ol (v) i ol (ma) 20420b-7 input i i (ma) v i (v) 20 -40 -60 -80 -2 -1 123 -20 45 -100 20420b-6 i oh (ma) v oh (v) 25 -50 -75 -100 -3 -2 -1 123 -25 -125 -150 45 output, high
16 MACH111-5/7/10/12/15 typical i cc characteristics v cc = 5 v, t a = 25 c the selected ?ypical?pattern is a 16-bit up/down counter. this pattern is programmed in each pal block and is capable of bein g loaded, enabled, and reset. maximum frequency shown uses internal feedback and a d-type register. high speed 150 125 100 75 50 25 0 0 10203040 5060708090 i cc (ma) frequency (mhz) low power 100 110 120 130 140 150 20420b-6
MACH111-5/7/10/12/15 17 typical thermal characteristics measured at 25 c ambient. these parameters are not tested. plastic q jc considerations the data listed for plastic q jc are for reference only and are not recommended for use in calculating junction temperatures. the heat-?w paths in plastic-encapsulated devices are complex, making the q jc measurement relative to a speci? location on the package surface. tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. furthermore, q jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. therefore, the measurements can only be used in a similar environment. the thermal measurements are taken with components on a six-layer printed circuit board. switching waveforms notes: 1. v t = 1.5 v. 2. input pulse amplitude 0 v to 3.0 v. 3. input rise and fall times 2 ns? ns typical. parameter symbol parameter description typ unit tqfp plcc q jc thermal impedance, junction to case 11 15 c/w q ja thermal impedance, junction to ambient 40 24 c/w q jma thermal impedance, junction to ambient with air ?w 200 lfpm air 35 18 c/w 400 lfpm air 33 17 c/w 600 lfpm air 32 16 c/w 800 lfpm air 31 15 c/w 20420b-7 combinatorial output t pd input, i/o, or feedback combinatorial output v t v t 20420b-8 20420b-9 registered output clock width v t input, i/o, or feedback registered output t s t co v t t h v t clock t wh clock t wl
18 MACH111-5/7/10/12/15 switching waveforms notes: 1. v t = 1.5 v. 2. input pulse amplitude 0 v to 3.0 v. 3. input rise and fall times 2 ns? ns typical. v t v t t arw v t t ar input, i/o, or feedback registered output clock t arr 20420b-10 asynchronous reset input, i/o, or feedback v t v t t apw v t t ap t apr registered output clock 20420b-11 asynchronous preset 20420b-12 output disable/enable v t v t outputs t er t ea v oh ?0.5 v v ol + 0.5 v input, i/o, or feedback
MACH111-5/7/10/12/15 19 key to switching waveforms switching test circuit* * switching several outputs simultaneously should be avoided for accurate measurement. speci?ation s 1 c l commercial measured output value r 1 r 2 t pd , t co closed 35 pf 300 w 390 w 1.5 v t ea z ? h: open z ? l: closed t er h ? z: open l ? z: closed 5 pf h ? z: v oh ?0.5 v l ? z: v ol + 0.5 v must be steady may change from h to l may change from l to h does not apply don? care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance ?ff state waveform inputs outputs ks000010-pal 20420b-13 c l output r 1 r 2 s 1 test point 5 v
20 MACH111-5/7/10/12/15 f max parameters the parameter f max is the maximum clock rate at which the device is guaranteed to operate. because the ?xibility inherent in programmable logic devices offers a choice of clocked ?p-?p designs, f max is speci?d for three types of synchronous designs. the ?st type of design is a state machine with feedback signals sent off-chip. this external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. the slowest path de?ing the period is the sum of the clock-to-output time and the input setup time for the external signals (t s + t co ). the reciprocal, f max , is the maximum frequency with external feedback or in conjunction with an equivalent speed device. this f max is designated ? max external. the second type of design is a single-chip state machine with internal feedback only. in this case, ?p-?p inputs are de?ed by the device inputs and ?p-?p outputs. under these conditions, the period is limited by the internal delay from the ?p-?p outputs through the internal feedback and logic to the ?p-?p inputs. this f max is designated ? max internal? a simple internal counter is a good example of this type of design; therefore, this parameter is sometimes called ? cnt. the third type of design is a simple data path application. in this case, input data is presented to the ?p-?p and clocked through; no feedback is employed. under these conditions, the period is limited by the sum of the data setup time and the data hold time (t s + t h ). however, a lower limit for the period of each f max type is the minimum clock period (t wh + t wl ). usually, this minimum clock period determines the period for the third f max , designated ? max no feedback.?all frequencies except f max internal are calculated from other measured ac parameters. f max internal is measured directly. logic register clk logic register clk t co t s t s f max internal (f cnt ) f max external 1/(t s + t co ) t s logic register clk f max no feedback; 1/(t s + t h ) or 1/(t wh + t wl ) (second chip) 20420b-14
MACH111-5/7/10/12/15 21 endurance characteristics the mach families are manufactured using vantis?advanced electrically erasable process. this technology uses an ee cell to replace the fuse link used in bipolar parts. as a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. endurance characteristics input/output equivalent schematics parameter symbol parameter description units test conditions t dr min pattern data retention time 10 years max storage temperature 20 years max operating temperature n max reprogramming cycles 100 cycles normal programming conditions v cc esd protection 1 k w input v cc 100 k w preload circuitry feedback input i/o v cc v cc 100 k w 1 k w 20420b-15
22 MACH111-5/7/10/12/15 power-up reset the mach devices have been designed with the capability to reset during system power-up. following power-up, all ?p-?ps will be reset to low. the output state will depend on the logic polarity. this feature provides extra ?xibility to the designer and is especially valuable in simplifying state machine initialization. a timing diagram and parameter table are shown below. due to the synchronous operation of the power-up reset and the wide range of ways v cc can rise to its steady state, two conditions are required to insure a valid power-up reset. these conditions are: 1. the v cc rise must be monotonic. 2. following reset, the clock input must not be driven from low to high until all applicable input and feedback setup times are met. parameter symbol parameter descriptions max unit t pr power-up reset time 10 m s t s input or feedback setup time see switching characteristics t wl clock width low 20420b-16 power-up reset waveform t pr t wl t s 4 v v cc power registered output clock
MACH111-5/7/10/12/15 23 development systems (subject to change) for more information on the products listed below, please consult the local vantis sales of?e. manufacturer software development systems vantis corporation p.o. box 3755 920 deguigne drive sunnyvale, ca 94088 (408) 732-0555 or 1(888) 826-8472 (vantis2) http://www.vantis.com machxl software vantis-abel software vantis-synario software aldec, inc. 3 sunset way, suite f henderson, nv 89014 (702) 456-1222 or (800) 487-8743 active-cad cadence design systems 555 river oaks pkwy san jose, ca 95134 (408) 943-1234 or (800) 746-6223 pic designer concept/composer synergy leapfrog/verilog-xl exemplar logic, inc. 815 atlantic avenue, suite 105 alameda, ca 94501 (510) 337-3700 leonardo galileo logic modeling 19500 nw gibbs dr. p.o. box 310 beaverton, or 97075 (800) 346-6335 smartmodel library mentor graphics corp. 8005 s.w. boeckman rd. wilsonville, or 97070-7777 (800) 547-3000 or (503) 685-7000 design architect, pldsynthesis ii autologic ii synthesizer, quicksim simulator, quickhdl simulator microsim corp. 20 fairbanks irvine, ca 92718 (714) 770-3022 microsim design lab plogic, plsyn minc inc. 6755 earl drive, suite 200 colorado springs, co 80918 (800) 755-fpga or (719) 590-1155 pldesigner-xl software model technology 8905 s.w. nimbus avenue, suite 150 beaverton, or 97008 (503) 641-1340 v-system/vhdl orcad, inc. 9300 s.w. nimbus avenue beaverton, or 97008 (503) 671-9500 or (800) 671-9505 orcad express synario ? design automation 10525 willows road n.e. p.o. box 97046 redmond, wa 98073-9746 (800) 332-8246 or (206) 881-6444 abel synario software
24 MACH111-5/7/10/12/15 vantis is not responsible for any information relating to the products of third parties. the inclusion of such information is n ot a representation nor an endorsement by vantis of these products. synopsys 700 e. middle?ld rd. mountain view, ca 94040 (415) 962-5000 or (800) 388-9125 fpga or design compiler (requires minc pldesigner-xl) vss simulator synplicity, inc. 624 east evelyn ave. sunnyvale, ca 94086 (408) 617-6000 synplify teradyne eda 321 harrison ave. boston, ma 02118 (800) 777-2432 or (617) 422-2793 multisim interactive simulator lasar veribest, inc. 6101 lookout road, suite a boulder, co 80301 (800) 837-4237 veribest pld viewlogic systems, inc. 293 boston post road west marlboro, ma 01752 (800) 873-8439 or (508) 480-0881 viewdraw, viewpld, viewsynthesis speedwave simulator, viewsim simulator, vcs simulator manufacturer test generation system acugen software, inc. 427-3 amherst st., suite 391 nashua, nh 03063 (603) 881-8821 atgen test generation software int gmbh busenstrasse 6 d-8033 martinsried, munich, germany (87) 857-6667 pldcheck 90 manufacturer software development systems
MACH111-5/7/10/12/15 25 approved programmers (subject to change) for more information on the products listed below, please consult the local vantis sales of?e. manufacturer programmer configuration advin systems, inc. 1050-l east duane ave. sunnyvale, ca 940 86 (408) 243-7000 or (800) 627-2456 bbs (408) 737-9200 fax (408) 736-2503 pilot-u40 pilot-u84 mvp bp microsystems 1000 n. post oak rd., suite 225 houston, tx 77055-7237 (800) 225-2102 or (713) 688-4600 bbs (713) 688-9283 fax (713) 688-0920 bp1200 bp1400 bp2100 bp2200 data i/o corporation 10525 willows road n.e. p.o. box 97046 redmond, wa 98073-9746 (800) 426-1045 or (206) 881-6444 bbs (206) 882-3211 fax (206) 882-1043 unisite model 2900 model 3900 autosite hi-lo systems 4f, no. 2, sec. 5, ming shoh e. road taipei, taiwan (886) 2-764-0215 fax (886) 2-756-6403 or tribal microsystems / hi-lo systems 44388 south grimmer blvd. fremont, ca 94538 (510) 623-8859 bbs (510) 623-0430 fax (510) 623-9925 all-07 flex-700 sms gmbh im grund 15 88239 wangen germany (49) 7522-97280 fax (49) 7522-972850 or sms usa 544 weddell dr. suite 12 sunnyvale, ca 94089 (408) 542-0388 sprint expert sprint optima multisite stag house silver court watchmead, welwyn garden city herfordshire uk al7 1lt 44-1-707-332148 fax 44-1-707-371503 stag quazar
26 MACH111-5/7/10/12/15 approved adapter manufacturers approved on-board isp programming tools system general 1603a south main street milpitas, ca 95035 (408) 263-6667 bbs (408) 262-6438 fax (408) 262-9220 or 3f, no. 1, alley 8, lane 45 bao shing road, shin diau taipei, taiwan (886) 2-917-3005 fax (886) 2-911-1283 turpro-1 turpro-1/fx turpro-1/tx manufacturer programmer configuration california integration coordinators, inc. 656 main street placerville, ca 95667 (916) 626-6168 fax (916) 626-7740 mach/pal programming adapters emulation technology, inc. 2344 walsh ave., bldg. f santa clara, ca 95051 (408) 982-0660 fax (408) 982-0664 adapt-a-socket programming adapters manufacturer programmer configuration corelis, inc. 12607 hidden creek way, suite h cerritos, california 70703 (310) 926-6727 jtagprog vantis corporation p.o. box 3755 920 deguigne drive sunnyvale, ca 94088 (408) 732-0555 or 1(888) 826-8472 (vantis2) http://www.vantis.com machpro manufacturer programmer configuration
MACH111-5/7/10/12/15 27 physical dimensions pl 044 44-pin plastic leaded chip carrier (measured in inches) top view seating plane .685 .695 .650 .656 pin 1 i.d. .685 .695 .650 .656 .026 .032 .050 ref .042 .056 .062 .083 .013 .021 .590 .630 .500 ref .009 .015 .165 .180 .090 .120 16-038-sq pl 044 da78 6-28-94 ae side view
28 MACH111-5/7/10/12/15 physical dimensions pqt044 44-pin thin quad flat pack (measured in millimeters) trademarks copyright ? 1998 vantis corporation. all rights reserved. amd is a registered trademark of advanced micro devices, inc. vantis, the vantis logo and combinations thereof, speedlocking and bus-friendly are trademarks, and mach, machxl, machpro and p al are registered trademarks of vantis corporation. other product names used in this publication are for identi?ation purposes only and may be trademarks of their respective comp anies. 1.00 ref. 1.20 max 11 ?13 11 ?13 0.80 bsc 44 1 0.95 1.05 11.80 12.20 9.80 10.20 11.80 12.20 9.80 10.20 0.30 0.45 16-038-pqt-2 pqt 44 7-11-95 ae

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